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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-30327-2E
MEMORY
LOW POWER SRAM CARD
PCMCIA Rel.2/JEIDA Ver.4 conformable
MB98A9083x/9093x/9103x/9113x-20
LOW POWER STATIC RANDOM ACCESS MEMORY CARD 256 K/512 K/1 M/2 M-BYTE s DESCRIPTION
The Fujitsu MB98A9083x, 9093x, 9103x and 9113x are Static Random Access Memory (SRAM) cards capable of storing and retrieving large amounts of data. The memory circuits are housed in a credit-card sized 68-pin package. Internal circuitry is protected by two metal panels, each one at the top and the bottom of the card, that help to reduce chip damage from electrostatic discharge. When the SRAM card is not powered by its system, an on-board, replaceable lithium battery (coin-type) is used to retain data. When the lithium battery must be replaced, rechargeable battery that are built in the SRAM card, maintain data. (See the BLOCK DIAGRAM for location of batteries.) A unique feature of the Fujitsu memory cards allows the user to organize the card into either an 8-bit or a 16-bit bus configuration. All cards are portable and operate on low power at high speed. In accordance with the Personal Computer Memory Card International Association (PCMCIA) and Japan Electrical Industry Development Association (JEIDA) industry standard specifications, SRAM cards offer additional EEPROM memory that is used to store attribute data. The attribute memory is an SRAM card option. (See page 3 for a description of the three available options.) * * * * * Credit card size: 85.6 mm (length) x 54.0 mm (width) x 3.3 mm (thick). PCMCIA/JEIDA conformed two-piece 68-pin connector (with a two-row built-in 68-pin receptacle) Low operating and standby power consumption Built-in, rechargeable batteries for data retention during lithium battery replacement Battery voltage detect and write protect function
s PACKAGE
(CRD 68P M04)
CRD-68P-M04
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MB98A9083x/9093x/9103x/9113x-20
s ATTRIBUTE MEMORY OPTIONS
PCMCIA and JEIDA standard memory cards from Fujitsu provide a separate EEPROM memory address space for recording fundamental card information. It is used by the card manufacturers to record basic configuration information such as device type, size, speed, etc. The attribute memory is selected by asserting the REG pin on the card interface. Option descriptions as follows:
OPTION 1: Attribute memory is not supported. REG Pin: Not Contacted
(JEIDA Ver.3 conformable) Part Number Main Memory Memory Device Access Time 200 ns 200 ns 200 ns 200 ns Attribute Memory Memory Device -- -- -- -- Access Time -- -- -- -- Memory Organization* 256 K x 8 bits/128 K x 16 bits 512 K x 8 bits/256 K x 16 bits 1 M x 8 bits/512 K x 16 bits 2 M x 8 bits/1 M x 16 bits
MB98A90831 1M SRAM x 2 pcs MB98A90931 1M SRAM x 4 pcs MB98A91031 1M SRAM x 8 pcs MB98A91131 1M SRAM x 16 pcs
OPTION 2: Attribute memory in a separate location is not supported. When the REG line is asserted, "FF" is output to the data bus to indicate that attribute data may be stored in main memory.
(PCMCIA Rel.2/JEIDA Ver.4 conformable) Part Number Main Memory Memory Device Access Time 200 ns 200 ns 200 ns 200 ns Attribute Memory Memory Device -- -- -- -- Access Time -- -- -- -- Memory Organization* 256 K x 8 bits/128 K x 16 bits 512 K x 8 bits/256 K x 16 bits 1 M x 8 bits/512 K x 16 bits 2 M x 8 bits/1 M x 16 bits
MB98A90832 1M SRAM x 2 pcs MB98A90932 1M SRAM x 4 pcs MB98A91032 1M SRAM x 8 pcs MB98A91132 1M SRAM x 16 pcs
OPTION 3: Attribute memory is supported. The data is stored in an 16K-bit EEPROM. When the REG line is asserted, data stored in EEPROM is output to the data bus.
Main Memory Memory Device Access Time 200 ns 200 ns 200 ns 200 ns (PCMCIA Rel.2/JEIDA Ver.4 conformable) Attribute Memory Memory Organization* Memory Device Access Time EEPROM x 1 pcs EEPROM x 1 pcs EEPROM x 1 pcs EEPROM x 1 pcs 300 ns 300 ns 300 ns 300 ns 256 K x 8 bits/128 K x 16 bits 512 K x 8 bits/256 K x 16 bits 1 M x 8 bits/512 K x 16 bits 2 M x 8 bits/1 M x 16 bits
Part Number
MB98A90833 1M SRAM x 2 pcs MB98A90933 1M SRAM x 4 pcs MB98A91033 1M SRAM x 8 pcs MB98A91133 1M SRAM x 16 pcs Note: * To be configured by user.
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MB98A9083x/9093x/9103x/9113x-20
Fig. 1 - MB98A9083x/9093x/9103x/9113x BLOCK DIAGRAM
VCC GND VBB*3
R WE OE
R = 100 K
R CE1 R CE2 R REG*4 A0 A20*2 A19*2 A18*2 A1
* * *
CS CE0
* * * * *
EEPROM*1 OE WE ADD I/O
WP SW
CS 1M SRAM x1 (MB98A9083x) x2 (MB98A9093x) x4 (MB98A9103x) x8 (MB98A9113x) ADD 17 ADD 1M SRAM x1 (MB98A9083x) x2 (MB98A9093x) x4 (MB98A9103x) x8 (MB98A9113x) CS
WE I/O TRANSCEIVER & BUFFER
INPUT DECODER & BUFFER
CE15 11
I/O
8
I/O
8
A17 RESET
WE RESET
VBB*3 VCC CC = 0.22 F BVD1 BVD2 CT SUPPLY VOLTAGE MONITOR IC C0 RESET VBAT1 VBAT2 VBAT2 RB
( Rechargeable ) Battery
D0
* *
(Replaceable ) Battery
VBAT1
D15 WP CD1 CD2
Notes: *1. EEPROM is only present in Option 3 (for attribute memory) SRAM cards. *2. See pins 47, 48 and 49 in "PIN ASSIGNMENTS." *3. VBB = VCC or VBAT1 or VBAT2. *4. N.C. terminal in MB98A9XX31 series.
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MB98A9083x/9093x/9103x/9113x-20
s PIN ASSIGNMENTS
MB98A9083x MB98A9093x MB98A9103x MB98A9113x Pin No. MB98A9083x MB98A9093x MB98A9103x MB98A9113x GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE N.C. VCC N.C. A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE N.C. VCC N.C. A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE N.C. VCC N.C. A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE N.C. VCC N.C. A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 62 63 64 65 66 67 68 GND CD1 D11 D12 D13 D14 D15 CE2 N.C. N.C. N.C. A17 N.C. N.C. N.C. N.C. VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. BVD2 BVD1 D8 D9 D10 CD2 GND GND CD1 D11 D12 D13 D14 D15 CE2 N.C. N.C. N.C. A17 A18 N.C. N.C. N.C. VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. BVD2 BVD1 D8 D9 D10 CD2 GND GND CD1 D11 D12 D13 D14 D15 CE2 N.C. N.C. N.C. A17 A18 A19 N.C. N.C. VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. BVD2 BVD1 D8 D9 D10 CD2 GND GND CD1 D11 D12 D13 D14 D15 CE2 N.C. N.C. N.C. A17 A18 A19 A20 N.C. VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. BVD2 BVD1 D8 D9 D10 CD2 GND
61 REG/N.C.* REG/N.C.* REG/N.C.* REG/N.C.*
* : N.C. terminal in MB98A9XX31 series.
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MB98A9083x/9093x/9103x/9113x-20
s PIN DESCRIPTIONS
Symbol A0 to A20 D0 to D15 Pin Name Address Input Data Input/Output Input/Output Input Input/Output Function Address Inputs, A0 to A20. Data Inputs/Outputs. The data bus size (8-bit or 16-bit) selected with CE1 and CE2. Active Low - Lower byte (D0 to D7) is selected for read/ write function of SRAM cards. Active Low - Upper byte (D8 to D15) is selected for read/write function of SRAM cards. Active Low - Attribute memory is selected for read/write function of identification data of SRAM cards. (N.C. or "FF" data or attribute data.) Active Low - Output enable for SRAM cards. Active Low - Write enable for SRAM cards. These pins detect if the card has been correctly inserted. Both pins are tied to GND internally. Write controller for SRAM cards This pin outputs the Protect / Non Protect status of "WP Switch". These pins indicate the battery condition of the SRAM cards. a) BVD1 = BVD2 = VOH -Battery voltage is a safe level. b) BVD2 = VOL, BVD1 = VOH -Battery voltage is lower than 2.65 V. Battery should be replaced. c)BVD1 = BVD2 = VOL -Battery voltage is lower than 2.37 V, or battery is not present. Power Supply Voltage (+5.0 V5%) System Ground
CE1
Card Enable for Lower Byte
Input
CE2
Card Enable for Upper Byte
Input
REG
Attribute Memory Select
Input
OE WE CD1, CD2
Output Enable Write Enable Card Detect
Input Input Output
WP BVD1
Write Protect Battery Voltage Detect 1
Output Output
BVD2
Battery Voltage Detect 2
Output
VCC GND N.C.
Power Supply Ground No Connection
-- -- --
s PIN LOCATIONS
Fig. 2 - BOTTOM VIEW (CONNECTOR SIDE) Front Side
34 68 Back Side
1 35
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MB98A9083x/9093x/9103x/9113x-20
s FUNCTIONAL TRUTH TABLE
MAIN MEMORY FUNCTION *1 (REG = VIH) CE2 H H H H H L L L L X H H H H H L L L L X CE1 H L L L L H H L L X H L L L L H H L L X A0 (Byte) X L H L H X X X X X X L H L H X X X X X OE X L L H*2 H*2 L H*2 L H*2 H X L L H*2 H*2 L H*2 L H*2 H WE X H H L L H L H L H X H H L L H L H L H WP L L L L L L L L L L H H H H H H H H H H Mode Standby Read (x8) Read (x8) Write (x8) Write (x8) Read (x8) Write (x8) Read (x16) Write (x16) Output Disable Standby Read (x8) Read (x8) Output Disable Output Disable Read (x8) Output Disable Read (x16) Output Disable Output Disable High-Z High-Z High-Z High-Z High-Z High-Z DOUT (Upper Byte) DIN (Upper Byte) DOUT DIN High-Z High-Z DOUT (Lower Byte) DOUT (Upper Byte) High-Z High-Z DOUT (Upper Byte) High-Z DOUT High-Z High-Z High-Z Data Input/Output D15 to D8 High-Z DOUT (Lower Byte) DOUT (Upper Byte) DIN (Lower Byte) DIN (Upper Byte) High-Z High-Z D7 to D0 WP SW NP NP NP NP NP NP NP NP NP NP P P P P P P P P P P
Notes: *1. H = VIH, L = VIL, X = Either VIL or VIH, WP SW = Write Protect Switch, NP = Non Protect, P = Protect *2. H-level is recommended though it is functionable at L-level.
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MB98A9083x/9093x/9103x/9113x-20
ATTRIBUTE MEMORY FUNCTION *1 (REG = VIL) *2 CE2 H H H H H L L L L X H H H H H L L L L X CE1 H L L L L H H L L X H L L L L H H L L X A0 (Byte) X L H L H X X X X X X L H L H X X X X X OE X L L H H L H L H H X L L H H L H L H H WE X H H L L H L H L H X H H L L H L H L H WP L L L L L L L L L L H H H H H H H H H H Mode Standby Read (x8) Read (x8) Write (x8) Write (x8) Read (x8) Write (x8) Read (x16) Write (x16) Output Disable Standby Read (x8) Read (x8) Output Disable Output Disable Read (x8) Output Disable Read (x16) Output Disable Output Disable H-level H-level High-Z DOUT *3 (Lower Byte) High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z H-level High-Z H-level X Data Input/Output D15 to D8 High-Z DOUT *3 (Lower Byte) H-level DIN (Lower Byte) X High-Z High-Z DOUT *3 (Lower Byte) DIN (Lower Byte) High-Z High-Z DOUT *3 (Lower Byte) H-level D7 to D0 WP SW NP NP NP NP NP NP NP NP NP NP P P P P P P P P P P
Notes: *1. H = VIH, L = VIL, X = Either VIL or VIH, WP SW = Write Protect Switch, NP = Non Protect, P = Protect *2. N.C. for MB98A90831, 90931, 91031 and 91131. *3. H-level is output for MB98A90832, 90932, 91032 and 91132.
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MB98A9083x/9093x/9103x/9113x-20
s ADDRESS CONFIGURATIONS *1 (MAIN MEMORY)
8-BIT BUS ORGANIZATION (CE1 = VIL, CE2 = VIH)
A20 to A0 0 0 0 0 1 1 1 1 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0001 0010 0011 1100 1101 1110 1111 CE2 H H H H H H H H CE1 L L L L L L L L D15 to D8 ----- ----- ----- ----- ----- ----- ----- ----- D7 to D0 0 Add. 1 Add. 2 Add. 3 Add. 2,097,148 Add. 2,097,149 Add. 2,097,150 Add. 2,097,151 Add.
8-BIT BUS ORGANIZATION (CE1 = VIH, CE2 = VIL) *2
A20 to A0 0 0 0 0 1 1 1 1 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 000x 001x 010x 011x 100x 101x 110x 111x CE2 L L L L L L L L CE1 H H H H H H H H D15 to D8 1 Add. 3 Add. 5 Add. 7 Add. 2,097,145 Add. 2,097,147 Add. 2,097,149 Add. 2,097,151 Add. D7 to D0 ----- ----- ----- ----- ----- ----- ----- -----
16-BIT BUS ORGANIZATION (CE1 = VIL, CE2 = VIL)
A20 to A0 0 0 0 0 1 1 1 1 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 000x 001x 010x 011x 100x 101x 110x 111x CE2 L L L L L L L L CE1 L L L L L L L L D15 to D8 1 Add. 3 Add. 5 Add. 7 Add. 2,097,145 Add. 2,097,147 Add. 2,097,149 Add. 2,097,151 Add. D7 to D0 0 Add. 2 Add. 4 Add. 6 Add. 2,097,144 Add. 2,097,146 Add. 2,097,148 Add. 2,097,150 Add.
Notes: *1. H = VIH, L = VIL, X = Either 0 or 1. *2. Even addresses are not available in this mode.
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MB98A9083x/9093x/9103x/9113x-20
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Supply Voltage Input Voltage Output Voltage Ambient Temperature Storage Temperature Symbol VCC VIN VOUT TA TSTG Value -0.5 to +6.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -10 to +60 *1 -20 to +65 *2 Unit V V V C C
Notes: *1. This value does not apply to the replaceable battery. *2. This value does not apply to the replaceable battery and data retention. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(Referenced to GND) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Ambient Temperature * Symbol VCC GND VIH VIL TA Min. 4.75 -- 2.4 -0.3 0 Typ. 5.0 0 -- -- -- Max. 5.25 -- VCC+0.3 0.8 55 Unit V V V V C
Note: * This value does not apply to the replaceable lithium battery. See VBAT1 in Fig.1. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
s CAPACITANCE
(TA = 25C, f = 1 MHz, VIN = VI/O = GND) Parameter Input Capacitance I/O Capacitance Notes *1 *2 Symbol CIN CI/O Min. -- -- Typ. -- -- Max. 50 50 Unit pF pF
Notes: *1. This value does not apply to CE1, CE2, REG and WE. *2. This value does not apply to BVD1, BVD2, CD1 and CD2.
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MB98A9083x/9093x/9103x/9113x-20
s DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Parameter Standby Supply Current Active Supply Current MB98A9083x/9093x Operating Supply Current MB98A9103x/9113x Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage *2 *3 *4 Notes *1 Symbol ISB1 ISB2 ICC1 ICC2 ILI ILI/O VOH VOL Condition CE1, CE2 VCC -0.2 V CE1, CE2 = VIH VIN = VIH or VIL CE1, CE2 = VIL, IOUT = 0 mA VIN = VIH or VIL, Cycle = Min Duty = 100%, IOUT = 0 mA OE = VIH during Write Cycle VIN = 0 V to VCC VOUT = 0 V to VCC, CE1, CE2 = VIH or OE = VIH or WE = VIL IOH = -1.0 mA IOL = 2.1 mA Min. -- -- -- -- -- -10 -10 2.4 -- Typ. -- -- -- -- -- -- -- -- -- Max. 0.5 5.0 50 180 240 10 10 -- 0.4 mA A A V V Unit mA mA mA
Notes: *1. This value does not apply to recharge current from system or replaceable lithium battery to rechargeable battery. *2. This value does not apply to CE1, CE2, REG and WE. *3. This value does not apply to BVD1, BVD2, CD1, CD2 and WP. *4. This value does not apply to CD1 and CD2.
Fig. 3 - AC TEST CONDITIONS * Output Load
+5 V R1 DOUT (I/O) CL*
* Input Pulse Levels: 0.6 V to 2.6 V * Input Pulse Rise and Fall Times: 5 ns (Transition between 0.8 V and 2.4 V) * Timing Reference Levels
Input: VIL = 0.8 V, VIH = 2.4 V Output: VOL = 0.8 V, VOH = 2.0 V R2 * Including Jig and stray capacitance
R1 Load I Load II 1.8 k 1.8 k
R2 990 990
CL 5 pF
Parameters Mesured tCLZ, tOLZ, tCHZ, tOHZ, tRCLZ, tROLZ, tRCHZ, tROHZ, tWLZ and tWHZ
100 pF All parameters except tCLZ, tOLZ, tCHZ, tOHZ, tRCLZ, tROLZ, tRCHZ, tROHZ, tWLZ and tWHZ
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MB98A9083x/9093x/9103x/9113x-20
s AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)
MAIN MEMORY READ CYCLE
Parameter Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Hold from Address Change Card Enable to Output Low-Z Output Enable to Output Low-Z Card Enable to Output High-Z Output Enable to Output High-Z Notes Symbol tRC tAA tCE tOE tOH tCLZ tOLZ tCHZ tOHZ Min. 200 -- -- -- 5 5 5 -- -- Max. -- 200 200 100 -- -- -- 50 50 Unit ns ns ns ns ns ns ns ns ns
*1, 2 *1, 2 *1, 2 *1, 2
ATTRIBUTE MEMORY READ CYCLE *3
Parameter Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Hold from Address Change Card Enable to Output Low-Z Output Enable to Output Low-Z Card Enable to Output High-Z Output Enable to Output High-Z Notes Symbol tRRC tRAA tRCE tROE tROH tRCLZ tROLZ tRCHZ tROHZ Min. 300 -- -- -- 5 5 5 -- -- Max. -- 300 300 150 -- -- -- 60 60 Unit ns ns ns ns ns ns ns ns ns
*1, 2 *1, 2 *1, 2 *1, 2
Notes: *1. Transition is measured at the point of 500 mV from steady state voltage. *2. This parameter is specified using Load II in Fig.3. *3. This parameter is for MB98A90833, 90933, 91033 and 91133.
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MB98A9083x/9093x/9103x/9113x-20
MAIN MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIH)
READ CYCLE 1: CE1 = OE = VIL, CE2 = VIH : x 8-bit Bus Organization
tRC Address (A0 to A20) VIH VIL tAA tOH VOH D0 to D7 VOL PREVIOUS DATA VALID DATA VALID
READ CYCLE 2: CE1 = VIH, CE2 = OE = VIL: x 8-bit Bus Organization CE1 = CE2 = OE = VIL: x 16-bit Bus Organization
tRC Address * (A1 to A20) VIH VIL tAA tOH D8 to D15 or D0 to D15 VOH PREVIOUS DATA VALID VOL DATA VALID
: Undefined
Note: * A0 = Either VIH or VIL.
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MB98A9083x/9093x/9103x/9113x-20
MAIN MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIH)
READ CYCLE 3: CE2 = VIH: x 8-bit Bus Organization
tRC Address (A0 to A20) VIH VIL tAA VIH CE1 VIL tCE tCLZ VIH OE VIL tOE tOLZ VOH D0 to D7 VOL High-Z DATA VALID tOHZ tCHZ
: Undefined
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MB98A9083x/9093x/9103x/9113x-20
MAIN MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIH)
READ CYCLE 4: CE1 = VIH: x 8-bit Bus Organization tRC Address * (A1 to A20) VIH VIL tAA VIH CE2 VIL tCE tCLZ VIH OE VIL tOE tOLZ VOH D8 to D15 VOL High-Z DATA VALID tOHZ tCHZ
READ CYCLE 5: CE1 = CE2: x 16-bit Bus Organization tRC Address * (A1 to A20) VIH VIL tAA CE1 = CE2 VIH VIL tCE tCLZ OE VIH VIL tOE tOLZ VOH D0 to D15 VOL High-Z DATA VALID tOHZ tCHZ
: Undefined
Note: * A0 = Either VIH or VIL.
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MB98A9083x/9093x/9103x/9113x-20
ATTRIBUTE MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIL) *1
READ CYCLE 1: CE1 = OE = VIL, CE2 = VIH : x 8-bit Bus Organization CE1 = CE2 = OE = VIL : x 16-bit Bus Organization tRRC Address *2 (A0 to A10) VIH VIL tRAA tROH D0 to D7 or D0 to D15 *3 VOH PREVIOUS DATA VALID VOL DATA VALID
READ CYCLE 2: CE2 = VIH: x 8-bit Bus Organization tRRC Address (A0 to A10) VIH VIL tRAA CE1 VIH VIL tRCE tRCLZ VIH OE VIL tROLZ VOH D0 to D7 VOL High-Z VALID DATA tROE tROHZ tRCHZ
: Undefined
Notes: *1. This timing diagram is for MB98A90833, 90933, 91033 and 91133. "FF" data is available on MB98A90832, 90932, 91032, and 91132 only. *2. A0 = Either VIH or VIL for a 16-bit bus organization. *3. H-level is output from D8 to D15.
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MB98A9083x/9093x/9103x/9113x-20
ATTRIBUTE MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIL) *1
READ CYCLE 3: CE1 = CE2: x 16-bit Bus Organization tRRC Address *2 (A0 to A10) VIH VIL tRAA VIH CE1 VIL tRCE tRCLZ VIH OE VIL tROLZ D0 to D7 *3 VOH VOL High-Z VALID DATA tROE tROHZ tRCHZ
: Undefined
Notes: *1. This timing diagram is for MB98A90833, 90933, 91033, and 91133. "FF" data is available on MB98A90832, 90932, 91032, and 91132 only. *2. A0 = Either VIH or VIL. *3. H-level is output from D8 to D15.
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MB98A9083x/9093x/9103x/9113x-20
MAIN MEMORY WRITE CYCLE *1
Parameter Write Cycle Time Address Valid to End of Write Chip Select to End of Write Data Valid to End of Write Data Hold Time Write Pulse Width Address Set Up Time Write Recovery Time Output Enable to Output Low-Z Output Enable to Output High-Z Write Enable to Output Low-Z Write Enable to Output High-Z Output Enable Set Up Time Output Enable Hold Time *2 *2 *2, 3 *2, 3 Notes Symbol tWC tAW tCW tDW tDH tWP tAS tWR tOLZ tOHZ tWLZ tWHZ tOES tOEH Min. 200 140 140 60 30 120 20 30 5 -- 5 -- 10 10 Max. -- -- -- -- -- -- -- -- -- 50 -- 50 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ATTRIBUTE MEMORY WRITE CYCLE *4
Parameter Byte Write Cycle Time Address Set Up Time Chip Enable Set Up Time Output Enable Set Up Time Write Pulse Width Address Hold Time Data Set Up Time Data Hold Time Chip Enable Hold Time Output Enable Hold Time Write Recovery Time End of Write to Output Time Number of Write per Byte Write Enable Hold Time Symbol tRWR tRAS tRCS tROES tRWP tRAH tRDS tRDH tRCH tROEH tRRE tRRBO N tRWEH Min. -- 20 0 20 100 50 50 20 0 20 50 -- 10000 10 Max. 10 -- -- -- -- -- -- -- -- -- -- 100 -- -- Unit ms ns ns ns ns ns ns ns ns ns ns ns Times ns
Notes: *1. If OE, CE1, and CE2 are in the Read Mode during this period, then the I/O pins are in the output state and the input signals of the phase opposite to the outputs must be applied. *2. Transition is measured at the point of 500 mV from steady state voltage. *3. This parameter is specified only during write cycle with OE = VIL and specified using Load II in Fig.3. *4. This parameter is for MB98A90833, 90933, 91033 and 91133.
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MB98A9083x/9093x/9103x/9113x-20
MAIN MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIH)
WRITE CYCLE 1: CE2 = VIH : x 8-bit Bus Organization
tWC Address (A0 to A20) VIH VIL tAW VIH OE VIL tCW VIH CE1 VIL tAS VIH WE VIL tOES VIH D0 to D7 VIL tWHZ tOHZ VOH D0 to D7 VOL High-Z tWLZ High-Z VALID DATA tOLZ tDW tDH tWP tOEH tWR
: Undefined
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MB98A9083x/9093x/9103x/9113x-20
MAIN MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIH)
WRITE CYCLE 2: CE1 = VIH : x 8-bit Bus Organization
tWC Address * (A1 to A20) VIH VIL tAW VIH OE VIL tCW VIH CE1 VIL tAS VIH WE VIL tOES VIH D8 to D15 VIL tWHZ tOHZ VOH D8 to D15 VOL High-Z tWLZ High-Z VALID DATA tOLZ tDW tDH tWP tOEH tWR
: Undefined
Note: * A0 = Either VIH or VIL.
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MB98A9083x/9093x/9103x/9113x-20
MAIN MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIH)
WRITE CYCLE 3: CE1 = CE2 : x 16-bit Bus Organization
tWC Address * (A1 to A20) VIH VIL tAW VIH OE VIL tCW VIH CE1 = CE2 VIL tAS VIH WE VIL tOES VIH D0 to D15 VIL tWHZ tOHZ VOH D0 to D15 VOL High-Z tWLZ High-Z VALID DATA tOLZ tDW tDH tWP tOEH tWR
: Undefined
Note: * A0 = Either VIH or VIL.
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MB98A9083x/9093x/9103x/9113x-20
MAIN MEMORY WRITE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIH)
WRITE CYCLE 4: CE2 = VIL : x 8-bit Bus Organization
tWC Address (A0 to A20) VIH VIL tAW VIH OE * VIL tAS VIH CE1 VIL tWP VIH WE VIL tDW VIH D0 to D7 VIL tCLZ VOH D0 to D7 VOL : Undefined High-Z tWHZ High-Z High-Z VALID DATA tDH tCW tWR
Note: * H-level is recommended for stable operation though the card is operable at L-level.
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MB98A9083x/9093x/9103x/9113x-20
MAIN MEMORY WRITE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIH)
WRITE CYCLE 5: CE1 = VIL : x 8-bit Bus Organization
tWC Address *1 (A1 to A20) VIH VIL tAW VIH OE *2 VIL tAS VIH CE2 VIL tWP VIH WE VIL tDW VIH D8 to D15 VIL tCLZ VOH D8 to D15 VOL : Undefined High-Z tWHZ High-Z High-Z VALID DATA tDH tCW tWR
Notes: *1. A0 = Either VIH or VIL. *2. H-level is recommended for stable operation though the card is operable at L-level.
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MB98A9083x/9093x/9103x/9113x-20
MAIN MEMORY WRITE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIH)
WRITE CYCLE 6: CE1 = CE2 : x 16-bit Bus Organization
tWC Address *1 (A1 to A20) VIH VIL tAW VIH OE *2 VIL tAS VIH CE1 = CE2 VIL tWP VIH WE VIL tDW VIH D0 to D15 VIL tCLZ VOH D0 to D15 VOL : Undefined High-Z tWHZ High-Z High-Z VALID DATA tDH tCW tWR
Notes: *1. A0 = Either VIH or VIL. *2. H-level is recommended for stable operation though the card is operable at L-level.
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MB98A9083x/9093x/9103x/9113x-20
ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIL) *1
WRITE CYCLE 1: CE2 = VIH : x 8-bit Bus Organization
Address (A0 to A10)
VIH VIL tRAS tRCS VIH tRAH tRCH
CE1 VIL tROES VIH OE VIL tRWP VIH WE VIL tRDW VIH D0 to D7 VIL High-Z VALID DATA tRW VOH D7 *2 VOL High-Z tRDH tRRE High-Z tRWEH tROEH
tRRBO
I7
O7
: Undefined
Notes: *1. This timing diagram is for MB98A90833, 90933, 91033, and 91133. "FF" data is available on MB98A90832, 90932, 91032, and 91132 only. *2. Data polling operation.
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MB98A9083x/9093x/9103x/9113x-20
ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIL) *1
WRITE CYCLE 2: CE1 = CE2 : x 16-bit Bus Organization
Address (A0 to A10)
VIH VIL tRAS tRCS VIH tRAH tRCH
CE1 = CE2 VIL tROES VIH OE VIL tRWP VIH WE VIL tRDW VIH D0 to D7 *2 VIL High-Z VALID DATA tRW VOH D7 *3 VOL High-Z tRDH tRRE High-Z tRWEH tROEH
tRRBO
I7
O7
: Undefined
Notes: *1. This timing diagram is for MB98A90833, 90933, 91033, and 91133. "FF" data is available on MB98A90832, 90932, 91032, and 91132 only. *2. Input levels of terminals D8 to D15 are not specified. *3. Data polling operation.
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MB98A9083x/9093x/9103x/9113x-20
ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIL) *1
WRITE CYCLE 3: CE2 = VIH : x 8-bit Bus Organization
Address (A0 to A10)
VIH VIL tRAS tRAH tRWP VIH tRWEH
CE1 VIL tROES VIH OE VIL tRCS VIH WE VIL tRDW VIH D0 to D7 VIL High-Z VALID DATA tRW VOH D7 *2 VOL High-Z tRDH tRRE High-Z tRCH tROEH
tRRBO
I7
O7
: Undefined
Notes: *1. This timing diagram is for MB98A90833, 90933, 91033, and 91133. "FF" data is available on MB98A90832, 90932, 91032, and 91132 only. *2. Data polling operation.
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MB98A9083x/9093x/9103x/9113x-20
ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIL) *1
WRITE CYCLE 4: CE1 = CE2 : x 16-bit Bus Organization
Address (A0 to A10)
VIH VIL tRAS tRAH tRWP VIH tRWEH
CE1 VIL tROES VIH OE VIL tRCS VIH WE VIL tRDW VIH D0 to D7 *2 VIL High-Z VALID DATA tRW VOH D7 *3 VOL High-Z tRDH tRRE High-Z tRCH tROEH
tRRBO
I7
O7
: Undefined
Notes: *1. This timing diagram is for MB98A90833, 90933, 91033, and 91133. "FF" data is available on MB98A90832, 90932, 91032, and 91132 only. *2. Input levels of terminals D8 to D15 are not specified. *3. Data polling operation.
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MB98A9083x/9093x/9103x/9113x-20
s POWER SUPPLY SEQUENCE CHARACTERISTICS
Parameter Detection Rising Voltage Detection Falling Voltage Battery Backup Recovery Time Data Retention Rising Time Battery Backup Set Up Time Data Retention Falling Time Symbol VINH VINL tBR tDRSU tBS tDRSF Min. 4.2 4.1 3.0 -- 10 0 Typ. 4.3 4.2 -- -- -- -- Max. 4.4 4.3 -- 0.5 -- -- Unit V V ms ms s ns
POWER-ON TIMING DIAGRAM
VINH (Min) VCC
VINH (Max) tDRSU
CE1, CE2 tBR Note*
VIH
Note: * Insertion or removal of the card is not recommended when VCC is greater than 0 V.
POWER-OFF TIMING DIAGRAM
VCC
VINL (Max)
VINL (Min)
VIH CE1, CE2 tDRSF tBS Note*
Note: * Insertion or removal of the card is not recommended when VCC is greater than 0 V.
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MB98A9083x/9093x/9103x/9113x-20
s UNIQUE FEATURES FOR SRAM CARD
1. REPLACEABLE BATTERIES FOR THE SRAM CARD
The battery used in the SRAM Card is a 3.0 V Lithium battery (coin type) with the following specifications: Diameter Thickness Weight Type : : : : 20.0 (mm) 2.5 (mm) 2.5 (g) Approx. CR2025, or equivalent
2. APPROXIMATE DATA RETENTION TIME WITH BATTERY SUPPORT ONLY
Part Number MB98A9083x MB98A9093x MB98A9103x MB98A9113x Approx. Data Retention Time * (TA = 20C) 7 years min. 15 years typ. 4 years min. 8 years typ. 2 years min. 4 years typ. 1 year min. 2 years typ.
* Determined by the memory density of the card; i.e., greater card density means less battery time.
3. REPLACING THE BATTERY IN THE SRAM CARD
a. Insert a slender pointed object, such as the end of a paper clip, into the hole on the upper side of the card. (See Fig. 4.) b. Release the battery holder by pressing the paper clip against the catch and pulling the battery holder straight out from the card. (The battery cavity is located at the top of the card. See Fig. 5.) When the battery holder is free from the card the battery will fall out. c. Replace the old battery with a fresh one. Be certain to match battery polarity to the + and - shown on the holder. d. Place the new battery into the holder, squeeze the holder containing the new battery tightly, and reinsert it into the battery cavity.
WARNING Battery MUST be replaced within 30 minutes* or data will be lost.
Note: *With condition that the SRAM card had been inserted into application system more than 10 minutes.
Fig. 4 - SRAM CARD DRAWING (TOP VIEW)
FU JI
IN SE
Fig.5 - BATTERY CASE DRAWING (TOP VIEW) Battery plus (+) PLUS minus (-) Battery Holder
Protect WP Switch
Side Hole
Battery Holder Card Body
TS
U
RT TH IS W AY
Non Protect
+
PULL OUT PUSH
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MB98A9083x/9093x/9103x/9113x-20
4. SPECIAL MONITORING PINS
4.1 BVD1, BVD2: Voltage Monitoring Pins These pins monitor the voltage of the battery which must be maintained at 2.65 V or greater for data retention. The condition of the battery is determined by reading the output signals on BVD1 and BVD2. 1. When BVD1=BVD2=VOH Battery voltage is sufficient to guarantee data retention; i.e., .2.65 V. 2. When BVD2=VOL, BVD1=VOH Battery voltage is lower than 2.65 V and should be replaced to safeguard data. 3. When BVD1=BVD2=VOL Battery voltage is less than 2.37 V: the level is dangerous. There is a possibility that data has not retained. *These functions operate over the Recommended Operating Conditions.
4.2 CD1, CD2: Card Detection Pins These pins detect the insertion of the card into the system. (See Fig. 6.) When the memory card has been correctly inserted, CD1 and CD2 are detected by the system. CD1, CD2 are tied to ground on the card side as shown in Fig. 6.
VCC CD1 (A) VCC CD2 (B) system side card side
4.3 WP: Write Protect Pins This pin monitors the position of the Write Protect switch. As shown in Fig. 7, the SRAM card has a Write Protect switch at the top of the card. To write to the card, the switch must be turned to the "Non Protect" position and the WE pin low. L-level is output on the WP pin. To prevent writing to the card, the switch must be turned to the "Protect" position. H-level is output on the WP pin. SRAM Card
- Fig. 6 -
Write Protect Switch
Non Protect Battery Holder WP Switch Protect Non Protect WP Pin H L - Fig. 7 -
Protect
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MB98A9083x/9093x/9103x/9113x-20
s PACKAGE DIMENSIONS
68-PIN MEMORY CARD (CASE No.: CRD-68P-M04)
2-R1.00(.039) 1.600.05 (.063.002)
Note: Dimensions comform with PCMCIA/JEIDA. (PC CARD STANDARD 95)
85.600.20(3.370.008) 10.50(.413)
1.000.05 (.039.002) 41.91 (1.650) REF 1.000.05 (.039.002) "A" 1.000.05 (.039.002) 10.50(.413) 3.300.10(.130.004) CONNECTOR PORTION 3.300.20(.130.008) CARD BODY 14.50(.571) 54.000.10 (2.126.004) 12.00(.472) 25.00 (.984)
Details of "A" part 1.270.10(.050.004)TYP.
1PIN 1.270.10 (.050.004)
C
1994 FUJITSU LIMITED K68004SC-5-2
Dimensions in mm (inches)
s DEVICE HANDLING PRECAUTIONS
This device in composed of fine electronic parts, so take care in handling or keeping it as below. * The card is made fine, so do not keep it in the high temperature nor high humiditly, place line in the direct sunshine nor near the heater. * The card should not be bent, scratched, dropped nor be shocked violently. * This device should never be taken a part. It could destroy the card or your personal computer hardware. * To help you handle this device safely, request us the device specifications when purchasing this device.
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MB98A9083x/9093x/9103x/9113x-20
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9704 (c) FUJITSU LIMITED Printed in Japan
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